Thank you for your honest answer!
I understand. It’s a shame, but what can I do? I’ll continue to figure this out myself.
By the way, while I wasn’t hearing from you, I discovered the YOSYS program in the Bianbu 2.2.1 repository. As I mentioned, I’m new to Verilog design, so I hadn’t thought about visualization programs. At some point, it occurred to me that I could try visualizing what I’d created in code. I’d seen similar code visualizations somewhere, maybe on YouTube or in some literature, but I’m not sure. I started searching on Google, and one of the suggestions mentioned YOSYS, which I found in the repository. Another suggestion was to use HDLBits.
When I tried to run YOSYS, it returned an error that clearly indicated a problem with one of the files. So this tool should be useful for troubleshooting.
So, I have a couple more questions for you:
-
What other tools are in the Bianbu 2.2.1 repository, and which ones do you recommend? Can you recommend any that I shouldn’t try?
-
Maybe I should also consider an FPGA test board. I’m not sure about that either; I’ve never worked with anything like that before. I haven’t had the opportunity, and I work in a different field. Can you recommend any boards that are guaranteed to work for my project?