Greetings, SpacemiT developers! I have a deep question about K1/M1 and K3. When you created their code, for example, Verilog, did you run any tests after creation? Are there any such tests publicly available? I’d like to run them, or some of them, on my Verilog code to check for any errors.
Summary
At this stage, I don’t have everything sorted out. There are a lot of bugs that I don’t yet know how to catch and fix.
Please don’t judge me too harshly, this is my third attempt at designing an rv64 kernel myself. And in this attempt, I decided to make it multi-core. My first two attempts were single-core, but it turned out to be much easier.
sorry, there is no publicly availabe tests we can provide.
Thank you for your honest answer!
I understand. It’s a shame, but what can I do? I’ll continue to figure this out myself.
By the way, while I wasn’t hearing from you, I discovered the YOSYS program in the Bianbu 2.2.1 repository. As I mentioned, I’m new to Verilog design, so I hadn’t thought about visualization programs. At some point, it occurred to me that I could try visualizing what I’d created in code. I’d seen similar code visualizations somewhere, maybe on YouTube or in some literature, but I’m not sure. I started searching on Google, and one of the suggestions mentioned YOSYS, which I found in the repository. Another suggestion was to use HDLBits.
When I tried to run YOSYS, it returned an error that clearly indicated a problem with one of the files. So this tool should be useful for troubleshooting.
So, I have a couple more questions for you:
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What other tools are in the Bianbu 2.2.1 repository, and which ones do you recommend? Can you recommend any that I shouldn’t try?
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Maybe I should also consider an FPGA test board. I’m not sure about that either; I’ve never worked with anything like that before. I haven’t had the opportunity, and I work in a different field. Can you recommend any boards that are guaranteed to work for my project?
