IME documentation for SEW=4

AI
1

I have carefully read the IME documentation and have run the sample program for vmadot. But there is missing information, particularly about SEW=4, which is mentioned in the documents.

  1. Do the K1 and K3 processors implement SEW=4?
  2. How is SEW=4 specified in a vsetvli instruction? The RVV 1.0 specification does not talk about it, though there are some unused bit combinations. The GNU assembler does not recognize a symbol e4, which is what I would expect to use.
  3. How are vector load and store coded?
  4. Is there a way to have matrices with dimensions other then MxM and Mx2M?
2

I’m not very familiar with IME implementation, so I’ll leave this question to someone more specialized. Just wanted to drop a link to the documentation I know of, in case anyone reading this thread wants to look it up.
docs-ai/en/architecture/ime_extension.md at main · spacemit-com/docs-ai

3

Thank you - those documents contain a lot of details that are not in “The RISC-V IME Set Specification” Version 20240422.

It turns out that the 4-bit operations are only in the A100 AI module, not in the A60 that is in the K1. So I can stop trying to find it!